The present invention generally relates to semiconductor manufacturing, and more particularly to fin field effect transistor devices (FinFET) having a wide unmerged epitaxially grown source drain region.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the substrate. As ICs continue to scale downward in size, fin field effect transistors (FinFETs), sometimes referred to as tri-gate structures, may be potential candidates for 32 nm node technology and beyond primarily because FinFETs may offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3D), fully depleted MOSFET devices having a fin structure formed from the substrate material. The gate structure may wrap a portion of the fin acting as the channel region. The portion of the fin not covered by the gate structure may define the source drain region of the semiconductor device.